1. Field of the Invention
The present invention relates to an information processing apparatus for reproducing and performing decoding and decode processing information of a recording medium in an optical disc device etc., and more particularly relates to the configuration of a binarization circuit unit used for reproducing the information.
2. Description of the Related Art
In a digital versatile disc (DVD) or other optical disc recording medium, a string of digital information is recorded with the direct current (DC) component suppressed. For this reason, in principle, if binarizing the reproduced RF signal while stripping the DC component by AC coupling, the information of the disc recording medium can be read out.
Specifically, the digital information recorded on the disc recording medium is read by an optical pick-up and subjected to predetermined processing in an RF amplifier to obtain a data string signal (RF signal). This data string signal (RF signal) is then binarized in a binarization circuit. The clock is extracted based on the RF signal binarized in the binarization circuit, supplied as digital binary data (RF data) to an eight to fourteen modulation (EFM) demodulation circuit, and demodulated.
Various proposals have been made regarding the binarization circuit used for reproducing the information of a disc recording medium in an optical disc device etc. (refer to for example Japanese Unexamined Patent Publication (Kokai) No. 11-134800).
FIG. 1 is a circuit diagram of an example of the configuration of a binarization circuit applied to an optical disc. This binarization circuit 1, as shown in FIG. 1, has a comparator 2, a low pass filter (LPF) 3, a slice level feedback amplifier 4, coupling capacitors C1 and C2 for eliminating the direct current component (DC component), resistor elements R1 to R4, variable resistor elements R5 and R6, and capacitors C3 to C6.
The binarization circuit 1 cuts the DC components from the differential RF signals by the coupling capacitors C1 and C2, inputs the results to the comparator 2 as signals RFAC and XRFAC, and binarizes them by the comparator 2. The binarized signals are supplied to a not illustrated PLL (Phase Locked Loop) and LPF 3. The PLL performs data reproduction. The LPF 3 integrates the binarized signals to generate an average value ASY1 of the binarized signals. The average value of the binarized signals, where an H level of the binarized signal is Vh, and an L level is V1, is given as Vc=(Vh−V1)/2 in an ideal state. In actuality, the value becomes different from the ideal state, so the level of the signal ASY1 does not coincide with the ideal average value Vc. By defining a voltage value obtained by amplifying the difference between the average value signal ASY1 and the ideal average value Vc as the slice level at the slice level feedback amplifier 4 and feeding back it to the comparator 2, the difference from the ideal state is controlled to become zero (0).
In this configuration, however, there have been the problems as pointed out below. All have been factors degrading the reproduction state.
Namely, when binarizing the RF signal, there was a difference in the propagation delays DLYR and DLYF at the time of the rising edge and at the time of the falling edge as shown in FIGS. 2A and 2B (the difference of the propagation delay between the time of the rising edge and the time of the falling edge will be referred to as the “propagation delay difference”). Further, as shown in FIG. 3, at an input node ASYO of the binarized signal to the LPF 3, it became a factor of waveform disturbance such as overshoot, undershoot, and waveform bluntness and error in the average value signal ASY1. Further, the reference voltage Vc for comparison with the average value signal ASY1 varied at the time of mass production and became a factor of error. In the same way as above, an input offset voltage of the feedback amplifier 4 varied at the time of mass production and became the factor of error. Further, the input offset voltage of the comparator 2 varied at the time of the mass production and became a factor of error. Further, due to temperature fluctuation, voltage fluctuation, aging, etc., various types of error factors fluctuated, so control at the time of shipping was difficult. Further, the feedback is controlled so that lengths of the H level and the L level have the same value at the node ASYG. However, the propagation delay difference in a path reaching the PLL from a branch point CMPOUT and the propagation delay difference in a path reaching the node ASYG from the branch point CMPOUT do not coincide, therefore, even in the optimum state at the node ASYO, the signal input to the PLL was not the optimum state. Namely, the feedback was not applied so that the signal became the best at the input point to the PLL.